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 74FR9245 9-Bit Bidirectional Transceiver with 3-STATE Outputs
April 1991 Revised August 1999
74FR9245 9-Bit Bidirectional Transceiver with 3-STATE Outputs
General Description
The 74FR9245 contains nine non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Current sinking capability is 64 mA on both the A and B Ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bidirectional transceiver. Transmit (active-HIGH) enables data from A Ports to B Ports; Receive (active-LOW) enables data from B Ports to A Ports. The Output Enable input, when HIGH, disables both A and B Ports by placing them in a High Z condition.
Features
s Non-inverting buffers s Bidirectional data path s A and B output sink capability of 64 mA, source capability of 15 mA s Guaranteed pin-to-pin skew, multiple output switching and 250 pf delay
Ordering Code:
Order Number 74FR9245SC 74FR9245MSA 74FR9245SPC Package Number M24B MSA24 N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
(c) 1999 Fairchild Semiconductor Corporation
DS010914
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74FR9245
Pin Descriptions
Pin Names OE T/R A0-A8 B0-B8 Description Output Enable Input (Active-LOW) Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs
Truth Table
Inputs OE L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Output T/R L H X Bus B Data to Bus A Bus A Data to Bus B High Z State
Logic Diagram
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74FR9245
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 1: Absolute maximum ratings are value beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IBVIT IIL VID IOD IIH + IOZH IIL + IOZL IOS ICEX IZZ ICCH ICCL ICCZ CIN Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current Input Leakage Test Output Circuit Leakage Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Input Capacitance 55 75 65 8.0 17.0 -100 4.75 2.4 2.0 0.55 5 7 100 -250 Min 2.0 0.8 -1.2 Typ Max Units V V V V V V A A A A V Min Min Min Min Max Max Max Max 0.0 VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA IOH = -3 mA (An, Bn) IOH = -15 mA (An, Bn) IOL = 64 mA (An, Bn) VIN = 2.7V (OE, T/R) VIN = 7.0V (OE, T/R) VIN = 5.5V (An, B n) VIN = 0.5V (OE, T/R) IID = 1.9 A All Other Pins Grounded 3.75 25 -150 -225 50 100 80 115 85 A A A mA A A mA mA mA pF pF 0.0 Max Max Max Max 0.0 Max Max Max 5.0 5.0 VIOD = 150 mV All Other Pins Grounded VOUT = 2.7V (An, Bn) VOUT = 0.5V (An, Bn) VOUT = 0.0V (An, Bn) VOUT = VCC (An, Bn) VOUT = 5.25V (An, Bn) All Outputs HIGH All Outputs LOW Outputs 3-STATE OE, T/R An, Bn
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74FR9245
AC Electrical Characteristics
TA = +25C Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Propagation Delay An to Bn or Bn to An Output Enable Time 1.0 1.0 2.7 2.7 1.7 1.7 VCC = +5.0V CL = 50 pF Typ 2.6 1.7 5.0 4.3 3.7 3.6 Max 3.9 3.9 6.5 6.5 6.0 6.0 TA = 0C to +70C VCC = +50V CL = 50 pF Min 1.0 1.0 2.7 2.7 1.7 1.7 Max 3.9 3.9 6.5 6.5 6.0 6.0 ns ns ns Units
Extended AC Electrical Characteristics
TA = 0C to +70C VCC = +50V Symbol Parameter CL = 50 pF Eight Outputs Switching (Note 3) Min tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL (Note 5) tOSLH (Note 5) tOST (Note 5) Pin-to-Pin Skew for HL Transitions Pin-to-Pin Skew for LH Transitions Pin-to-Pin Skew for HL/LH Transitions Output Disable Time Propagation Delay An to Bn or Bn to An Output Enable Time 1.0 1.0 2.7 2.7 1.7 1.7 Max 5.8 5.8 8.8 8.8 7.0 7.0 2.0 1.0 3.0 Min 2.2 2.2 Max 8.1 8.1 ns ns ns ns ns ns TA = 0C to +70C VCC = +50V CL = 250 pF (Note 4) Units
Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase, i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc. Note 4: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 5: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or HIGH-to-LOW and/or LOW-to-HIGH (tOST). Specifications guaranteed with all outputs switching in phase.
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74FR9245
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA24
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74FR9245 9-Bit Bidirectional Transceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com


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